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ICS580-01 Glitch-Free Clock Multiplexer
Description
The ICS580-01 is a clock multiplexer (mux) designed to switch between 2 clock sources with no glitches or short pulses. The operation of the mux is controlled by an input pin but the part can also be configured to switch automatically if one of the input clocks stops. The part also provides clock detection by reporting when an input clock has stopped. For a clock mux with zero delay and smooth switching, see either the ICS581-01 or ICS581-02.
Features
* Packaged in 16 pin narrow (150 mil) SOIC * No short pulses or glitches on output * Operates to 200 MHz * Does not add jitter or phase noise to the clock * User controlled or automatic switching * Low skew outputs * Clock detect feature * Ideal for systems with backup or redundant clocks * Selectable timeouts for clock detection * Separate supply voltages allow power supply voltage translation * Operates to 2.5 V
Block Diagram
VDDI VDDC
CLK1 INB INA SELB
OE2
1
OE1
0
CLK2
Transition Detector
OE3
NO_INA
Transition Detector
OE4
NO_INB
DIV
Timer
1 Revision 030300 Printed 11/28/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126* (408) 295-9800tel * www.icst.com
MDS 580-01 A
ICS580-01 Glitch-Free Clock Multiplexer
Pin Assignment
SELB DIV VDDI INA INB GND OE4 OE3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 OE1 VDDC CLK1 CLK2 NO_INA NO_INB GND OE2
Timeout Selection
DIV 0 1 Nominal Timeout 600 ns 75 ns
Pin Descriptions
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name SELB DIV VDDI INA INB GND OE4 OE3 OE2 GND NO_INB NO_INA CLK2 CLK1 VDDC OE1 Type I I P I I P I I I P O O O O P I Description Mux select. Selects INB when high. Internal pull-up. Time out select. See table above. Internal pull-up. Supply for input clocks only. Can be higher than VDDC. Input Clock A. Input Clock B. Connect to ground. Output Enable. Tri-states NO_INB when low. Internal pull-up. Output Enable Tri-states NO_INA when low. Internal pull-up. Output enable. Tri-states CLK2 when low. Internal pull-up. Connect to ground. Goes high when clock on INB stops. Goes high when clock on INA stops. Clock 2 Output. Low skew compared to CLK1. Clock 1 Output. Low skew compared to CLK2. Main chip supply. Output clocks amplitude will match this VDD. Output Enable. Tri-states CLK1 when low. Internal pull-up.
Key: I = Input; O = output; P = power supply connection
2 Revision 030300 Printed 11/28/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126* (408) 295-9800tel * www.icst.com
MDS 580-01 A
ICS580-01 Glitch-Free Clock Multiplexer
Device Operation and Applications The ICS580-01 consists of a glitch free mux between INA and INB controlled by SELB. The device is designed to switch between 2 clocks, whether running or not. In the first example, clocks are running on both INA and INB. When SELB changes, the output clock goes low after 3 cycles of the output clock (nominally). The output then stays low for 3 cycles of the new input clock (nominally) and then starts with the new input clock. This is shown in Figure 1. Figure 1
INA INB SELB CLK1, 2
In the second example, one of the inputs was selected and running but has since stopped (either high or low). This is indicated by either NO_INA or NO_INB going high depending on whether INA or INB has stopped. These signals go high following a selectable time-out period after the clock has stopped. The timeout period is determined by the DIV input pin. The SELB pin is now changed to select the new input clock which is running. The output clock immediately goes low and stays low for 3 cycles of the new input clock and then starts with the new input clock. Figure 2 shows an example of this. Figure 2
INA INB SELB Timeout NO_INA CLK1, 2
3 Revision 030300 Printed 11/28/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126* (408) 295-9800tel * www.icst.com
MDS 580-01 A
ICS580-01 Glitch-Free Clock Multiplexer
In the third example, the ICS580-01 is configured to automatically switch clocks when an an input stops. The clock that could stop is connected to INA while the backup, always running, clock is connected to INB. The output NO_INA is connected to SELB. This means that when the clock on INA stops, NO_INA goes high selecting the clock on INB which is muxed to the output after 3 cycles. When the clock on INA restarts, NO_INA immediately goes low, selecting the clock on INA. The output then switches in the manner described in the first example. The circuit diagram in Figure 3 shows a typical connection for this example. Note that CLK2 and NO_INB are unused and so are disabled by grounding OE2 and OE4. A 33 series termination resistor is used on the clock output and 2 decoupling capacitors of 0.01F are used. All other inputs are left floating and are therefore pulled high by the on-chip pull-ups. Figure 3
VDD
SELB DIV VDDI 0.01F Normal Clock Backup Clock INA INB GND OE4 OE3
OE1 VDDC 0.01F CLK1 33 CLK2 NO_INA NO_INB GND OE2 Output Clock
Output Enable Each output has a dedicated output enable pin. If an output is unused, it should be tri-stated by tying the appropriate output enable pin to ground. External Components The ICS580-01 requires two 0.01F decoupling capacitors, one between VDDI and GND and one between VDDC and GND. Series termination resistors of 33 can be used on CLK1 and CLK2. Split Power Supplies The VDDI pin provides the power for the INA and INB input buffers only. All the other inputs and the rest of the chip are connected to VDDC. This allows for supply voltage translation. For example, INA and INB could be 5 V clocks (VDDI=5 V) and the rest of the chip could use a 3.3 V supply on VDDC giving 3.3 V output clocks. For correct operation VDDI must always be greater than or equal to VDDC. 4 Revision 030300 Printed 11/28/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126* (408) 295-9800tel * www.icst.com
MDS 580-01 A
ICS580-01 Glitch-Free Clock Multiplexer
Electrical Specifications
Parameter Conditions Referenced to GND Referenced to GND Industrial temperature Max of 10 seconds Minimum Typical Maximum 7 VDD+0.5 70 85 260 150 5.5 5.5 VDDI (VDDC/2)-1 VDDC 0.8 0.5 6 70 250 4 1/timeout 1/timeout 1/timeout 4 5 6 350 1000 1500 40 110 200 270 220 180 8 10 12 700 2000 3000 80 210 400 1.5 1.5 250 Units V V C C C C V V V V V V V V mA mA k pF MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ps
ABSOLUTE MAXIMUM RATINGS
Supply voltage, VDD Inputs and Clock Outputs Ambient Operating Temperature Ambient Operating Temperature, I version Soldering Temperature Storage temperature Operating Voltage, VDDC Operating Voltage, VDDI Input High Voltage, VIH, note 3 Input Low Voltage, VIL, note 3 Input High Voltage, VIH Input Low Voltage, VIL Output High Voltage, VOH Output Low Voltage, VOL Operating Supply Current, IDD Short Circuit Current On-chip pull-up resistor, non-clock inputs Input Capacitance Input Frequency, INA and INB. Note 1. -0.5 0 -40 -65 2.5 VDDC (VDDC/2)+1 VDDC/2 VDDC/2 2 VDDC-0.5
DC CHARACTERISTICS (VDDC = VDDI = 3.3 V unless noted)
INA and INB only INA and INB only Non-clock inputs Non-clock inputs IOH=-12mA IOL=12mA 50 MHz inputs, no load Pull-up to VDDC
AC CHARACTERISTICS (VDDC = VDDI = 3.3 V unless noted)
VDDC = 5 V VDDC = 3.3 V VDDC = 2.7 V VDDC = 5 V VDDC = 3.3 V VDDC = 2.7 V VDDI = 5 V VDDI = 3.3 V VDDI = 2.7 V VDDI = 5 V VDDI = 3.3 V VDDI = 2.7 V
Propagation Delay, INA or INB to output
Transition Detector Timeout, DIV=0
Transition Detector Timeout, DIV=1
175 500 750 20 55 100
Output Clock Rise Time Output Clock Fall Time Output Clock Skew, CLK1 to CLK2
Note 2
-250
0
Note 1. Frequencies less than the minimum may cause a timeout, which will not guarantee glitch-free switching unless the clock is actually stopped. Note 2. Assumes identically loaded outputs with identical rise times, measured at VDD/2. Note 3. Output duty cycle is set by duty cycle of input clock at VDDC/2.
5 Revision 030300 Printed 11/28/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126* (408) 295-9800tel * www.icst.com
MDS 580-01 A
ICS580-01 Glitch-Free Clock Multiplexer
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC publication no. 95.) 16 pin SOIC narrow
Symbol A A1 B C D E e H L Inches Min Max 0.059 0.069 0.004 0.0098 0.013 0.020 0.007 0.0098 0.386 0.394 0.150 0.157 .050 BSC 0.228 0.244 0.016 0.05 Millimeters Min Max 1.50 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.80 4.00 1.27 BSC 5.80 6.20 0.41 1.27
E
H
D A1 e B C L A
Ordering Information
Part/Order Number ICS580M-01 ICS580M-01T ICS580M-01I ICS580M-01IT Marking ICS580M-01 ICS580M-01 ICS580M-01I ICS580M-01I Package 16 pin SOIC 16 pin SOIC on tape and reel 16 pin SOIC 16 pin SOIC on tape and reel Temperature 0 to 70 C 0 to 70 C -40 to 85C -40 to 85C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
6 Revision 030300 Printed 11/28/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126* (408) 295-9800tel * www.icst.com
MDS 580-01 A

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